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September 2006 HYS72T32000HP-[3S/3.7]-A HYS72T64001HP-[3S/3.7]-A HYS72T64020HP-[3S/3.7]-A 240-Pin Registered DDR2 SDRAM Modules DDR2 SDRAM RDIMM SDRAM RoHs Compilant Internet Data Sheet Rev. 1.01 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules HYS72T32000HP-[3S/3.7]-A, HYS72T64001HP-[3S/3.7]-A, HYS72T64020HP-[3S/3.7]-A Revision History: 2006-09, Rev. 1.01 Page All All 24 Subjects (major changes since last revision) Qimonda update Adapted internet edition Modified AC Timing Parameters Previous Revision: 2006-03, Rev. 1.0 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com qag_techdoc_rev400 / 3.2 QAG / 2006-07-21 03292006-ZZHP-PR83 2 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 1 Overview This chapter gives an overview of the 240-pin Registered DDR2 SDRAM Modules with parity bit product family and describes its main characteristics. 1.1 Features * Programmable CAS Latencies (3, 4 and 5), Burst Length (4 & 8) and Burst Type * Auto Refresh (CBR) and Self Refresh * Average Refresh Period 7.8 s at a T lower than 85 C, 3.9 s between 85 C and 95 C * Programmable self refresh rate via EMRS2 setting * All inputs and outputs SSTL_18 compatible * Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) * Serial Presence Detect with E2PROM * Based on standard reference layouts Raw Cards "F", "G" and "H" * RDIMM with parity bit Dimensions (nominal): 30.00 mm high, 133.35 mm wide * RoHS compliant products1) * 240-pin PC2-5300 and PC2-4200 DDR2 SDRAM memory modules. * One rank in 32M x 72, 64M x 72 and two rank in 64M x 72 module organization and 32M x 8, 64M x 4 chip organization * 256M, 512 MByte modules are built with 256-Mbit DDR2 SDRAMs in P-TFBGA-60 chipsize packages. * Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply * All speed grades faster than DDR2-400 comply with DDR2-400 timing specifications as well. * Registered DIMM with Parity bit for address and control bus TABLE 1 Performance table for -3S Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time -3S PC2-5300 5-5-5 Unit -- MHz MHz MHz ns ns ns ns fCK5 fCK4 fCK3 tRCD tRP tRAS tRC 333 266 200 15 15 45 60 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Rev. 1.01, 2006-09 03292006-ZZHP-PR83 3 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules TABLE 2 Performance table for -3.7 Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time -3.7 PC2-4200 4-4-4 Unit -- MHz MHz MHz ns ns ns ns fCK5 fCK4 fCK3 tRCD tRP tRAS tRC 266 266 200 15 15 45 60 TABLE 3 Performance table for -5 Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time -5 PC2-3200 3-3-3 Units -- MHz MHz MHz ns ns ns ns fCK5 fCK4 fCK3 tRCD tRP tRAS tRC 200 200 200 15 15 40 55 Rev. 1.01, 2006-09 03292006-ZZHP-PR83 4 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 1.2 Description devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial EPROM device using the 2-pin IC protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. The QIMONDA HYS72T[32/64]xxxHP-[3S/3.7]-A module family are Registered DIMM (RDIMM with parity) with 30.00 mm height based on DDR2 technology. DIMMs are available as ECC modules in 32M x 72 (256 Mbyte) and 64M x 72 (512 MByte) organization and density, intended for mounting into 240-Pin connector sockets. The memory array is designed with 256-Mbit Double-DataRate-Two (DDR2) Synchronous DRAMs. All control and address signals are re-driven on the DIMM using register TABLE 4 Ordering Information for RoHS Compliant Products Product Type1) PC2-5300 HYS72T32000HP-3S-A HYS72T64001HP-3S-A HYS72T64020HP-3S-A PC2-4200 HYS72T32000HP-3.7-A HYS72T64001HP-3.7-A HYS72T64020HP-3.7-A 256MB 1Rx8 PC2-4200P-444-12-F0 512MB 1Rx4 PC2-4200P-444-12-H0 512MB 2Rx8 PC2-4200P-444-12-G0 1 Rank, ECC 1 Rank, ECC 2 Rank, ECC 256 Mbit (x8) 256 Mbit (x4) 256 Mbit (x8) 256MB 1Rx8 PC2-5300P-555-12-F0 512MB 1Rx4 PC2-5300P-555-12-H0 512MB 2Rx8 PC2-5300P-555-12-G0 1 Rank, ECC 1 Rank, ECC 2 Rank, ECC 256 Mbit (x8) 256 Mbit (x4) 256 Mbit (x8) Compliance Code2) Description SDRAM Technology 1) All Product Types end with a place code, designating the silicon die revision. Example: HYS72T64020HP-3.7-A, indicating Rev. "A" dies are used for DDR2 SDRAM components. For all QIMONDA DDR2 module and component nomenclature see Chapter 6 of this data sheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2-4200P-444-12-G0", where 4200P means Very Low Profile Registered DIMM modules with 4.26 GB/sec Module Bandwidth and "444-12" means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced on the Raw Card "G" TABLE 5 Address Format DIMM Density 256 MB 512 MB 512 MB Module Organization 32M x 72 64M x 72 64M x 72 Memory Ranks 1 1 2 ECC/ Non-ECC ECC ECC ECC # of SDRAMs 9 18 18 # of row/bank/columns bits 13/2/10 13/2/11 13/2/10 Raw Card F H G Rev. 1.01, 2006-09 03292006-ZZHP-PR83 5 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules TABLE 6 Components on Modules Product Type1) HYS72T32000HP HYS72T64001HP HYS72T64020HP DRAM Components1) HYB18T256800AF HYB18T256400AF HYB18T256800AF DRAM Density 256 Mbit 256 Mbit 256Mbit DRAM Organization 32M x 8 64M x 4 32M x 8 Note2) 1) Green Product 2) For a detailed description of all available functions of the DRAM components on these modules see the component data sheet. Rev. 1.01, 2006-09 03292006-ZZHP-PR83 6 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 2 2.1 Pin Configuration Pin Configuration and Table 9 respectively. The pin numbering is depicted in Figure 1. This chapter contains the pin configuration and block diagrams. The pin configuration of the Registered DDR2 SDRAM DIMM is listed by function in Table 7 (240 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 8 TABLE 7 Pin Configuration of RDIMM Ball No. Clock Signals 185 186 52 171 CK0 CK0 CKE0 CKE1 NC Control Signals 193 76 S0 S1 NC 192 74 73 18 Address Signals 71 190 54 BA0 BA1 BA2 NC I I I I SSTL SSTL SSTL SSTL Bank Address Bus 2 Not Connected Bank Address Bus 1:0 RAS CAS WE RESET I I NC I I I I SSTL SSTL -- SSTL SSTL SSTL CMOS Register Reset Chip Select Rank 1:0 Note: 2-Ranks module Not Connected Note: 1-Rank module Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) I I I I NC SSTL SSTL SSTL SSTL -- Clock Enables 1:0 Note: 2-Ranks module Not Connected Note: 1-Rank module Clock Signal CK0, Complementary Clock Signal CK0 Name Pin Type Buffer Type Function Rev. 1.01, 2006-09 03292006-ZZHP-PR83 7 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules Ball No. 188 183 63 182 61 60 180 58 179 177 70 57 176 196 174 173 Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 A13 NC A14 NC A15 NC Pin Type I I I I I I I I I I I I I I I NC I NC I NC Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- SSTL -- SSTL -- Function Address Bus 12:0, Address Signal 10/AutoPrecharge Address Signal 13 Not Connected Address Signal 14 Not Connected Address Signal 14 Not Connected Rev. 1.01, 2006-09 03292006-ZZHP-PR83 8 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules Ball No. Data Signals 3 4 9 10 122 123 128 129 12 13 21 22 131 132 140 141 24 25 30 31 143 144 149 150 33 34 39 40 152 153 158 159 80 81 86 87 199 200 205 Name Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Function DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 Data Bus 63:0 Rev. 1.01, 2006-09 03292006-ZZHP-PR83 9 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules Ball No. 206 89 90 95 96 208 209 214 215 98 99 107 108 217 218 226 227 110 111 116 117 229 230 235 236 Check Bits 42 43 48 49 161 162 167 168 Name DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Function Data Bus 63:0 Check Bits 7:0 Rev. 1.01, 2006-09 03292006-ZZHP-PR83 10 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules Ball No. Data Strobe Bus 7 6 16 15 28 27 37 36 84 83 93 92 105 104 114 113 46 45 125 126 134 135 146 147 155 156 202 203 211 212 223 224 232 233 164 165 Name Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Function DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 DQS8 DQS8 DQS9 DQS9 DQS10 DQS10 DQS11 DQS11 DQS12 DQS12 DQS13 DQS13 DQS14 DQS14 DQS15 DQS15 DQS16 DQS16 DQS17 DQS17 Data Strobes 17:0 Rev. 1.01, 2006-09 03292006-ZZHP-PR83 11 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules Ball No. Data Mask 125 134 146 155 202 211 223 232 164 EEPROM 120 119 239 240 101 Parity 55 Power Supplies 1 238 51, 56, 62, 72, 75, 78, 170, 175,, 181, 191, 194 53, 59, 64, 67, 69, 172, 178, 184,, 187, 189, 197 Name Pin Type I I I I I I I I I I I/O I I I O I AI PWR PWR Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL CMOS OD CMOS CMOS CMOS CMOS CMOS -- -- -- Function DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 SCL SDA SA0 SA1 SA2 ERR_OUT PAR_IN Data Masks 8:0 Note: x8 based module Serial Bus Clock Serial Bus Data Serial Address Select Bus 2:0 Parity bits VREF VDDSPD VDDQ I/O Reference Voltage EEPROM Power Supply I/O Driver Power Supply VDD PWR -- Power Supply 2, 5, 8, 11, 14, 17, VSS 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 65, 66, 79, 82, 85, 88, 91, 94, 97, 100, 103, 106, 109, 112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237 GND -- Ground Plane Rev. 1.01, 2006-09 03292006-ZZHP-PR83 12 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules Ball No. Other Pins Name Pin Type NC Buffer Type -- Function 19, 55, 68, 102, NC 137, 138, 173, 220, 221 195 77 ODT0 ODT1 NC Not connected I I NC SSTL SSTL -- On-Die Termination Control 1:0 Note: 2-Ranks module Note: 1-Rank modules TABLE 8 Abbreviations for Buffer Type Abbreviation SSTL CMOS OD Description Serial Stub Terminated Logic (SSTL_18) CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. TABLE 9 Abbreviations for Pin Type Abbreviation I O I/O AI PWR GND NU NC Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Usable Not Connected Rev. 1.01, 2006-09 03292006-ZZHP-PR83 13 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules FIGURE 1 Pin Configuration for RDIMM (240 pins) Rev. 1.01, 2006-09 03292006-ZZHP-PR83 14 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 3 3.1 Electrical Characteristics Absolute Maximum Ratings TABLE 10 Absolute Maximum Ratings This chapter lists the electrical characteristics. Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 10 at any time. Symbol Parameter Rating Min. Max. +2.3 +2.3 +2.3 +2.3 Unit Note Storage Temperature -55 +100 1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV. 2) Storage Temperature is the case surface temperature on the center/top side of the DRAM. VDD VDDQ VDDL VIN, VOUT TSTG Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS -1.0 -0.5 -0.5 -0.5 V V V V C 1) 1)2) 1)2) 1) 1)2) Attention: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TABLE 11 DRAM Component Operating Temperature Range Symbol Parameter Rating Min. Max. 95 C 1)2)3)4) Unit Note TOPER Operating Temperature 0 1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95 C under all other specification parameters. 3) Above 85 C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 s 4) When operating this product in the 85 C to 95 C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to "1". When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50% Rev. 1.01, 2006-09 03292006-ZZHP-PR83 15 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 3.2 DC Operating Conditions TABLE 12 Operating Conditions This chapter describes the DC characteristics. Parameter Symbol Values Min. Max. +65 +95 +100 +105 90 Unit Note Operating temperature (ambient) DRAM Case Temperature Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative) 1) 2) 3) 4) TOPR TCASE TSTG PBar 0 0 - 50 +69 10 C C C kPa % 5) 1)2)3)4) HOPR DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. Within the DRAM Component Case Temperature Range all DRAM specifications will be supported Above 85 C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s When operating this product in the 85 C to 95 C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to "1". When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%. 5) Up to 3000 m. TABLE 13 Supply Voltage Levels and DC Operating Conditions Parameter Symbol Values Min. Device Supply Voltage Output Supply Voltage Input Reference Voltage SPD Supply Voltage DC Input Logic High DC Input Logic Low Typ. 1.8 1.8 0.5 x VDDQ -- -- -- Max. 1.9 1.9 0.51 x VDDQ 3.6 V V V V V V 3) 1) 2) Unit Note In / Output Leakage Current -5 -- 5 A 1) Under all conditions, VDDQ must be less than or equal to VDD 2) Peak to peak AC noise on VREF may not exceed 2% VREF (DC).VREF is also expected to track noise in VDDQ. 3) Input voltage for any connector pin under test of 0 V VIN VDDQ + 0.3 V; all other pins at 0 V. Current is per pin VDD VDDQ VREF VDDSPD VIH(DC) VIL (DC) IL 1.7 1.7 0.49 x VDDQ 1.7 VREF + 0.125 - 0.30 VDDQ + 0.3 VREF - 0.125 Rev. 1.01, 2006-09 03292006-ZZHP-PR83 16 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 3.3 AC Characteristics This chapter describes the AC characteristics. 3.3.1 Speed Grades Definitions TABLE 14 Speed Grade Definition Speed Bins for DDR2-667D This chapter contains the Speed Grade Definition tables. Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol DDR2-667D -3S 5-5-5 Min. 5 3.75 3 45 60 15 15 Max. 8 8 8 70000 -- -- -- Unit Notes tCK -- ns ns ns ns ns ns ns 1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4) tCK tCK tCK tRAS tRC tRCD tRP 1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI. TABLE 15 Speed Grade Definition Speed Bins for DDR2-533C Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time Symbol DDR2-533C -3.7 4-4-4 Min. 5 3.75 3.75 45 60 Max. 8 8 8 70000 -- Unit Note tCK -- ns ns ns ns ns 1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) tCK tCK tCK tRAS tRC Rev. 1.01, 2006-09 03292006-ZZHP-PR83 17 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter RAS-CAS-Delay Row Precharge Time Symbol DDR2-533C -3.7 4-4-4 Min. 15 15 Max. -- -- Unit Note tCK -- ns ns 1)2)3)4) 1)2)3)4) tRCD tRP 1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI. Rev. 1.01, 2006-09 03292006-ZZHP-PR83 18 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 3.3.2 AC Timing Parameters TABLE 16 Timing Parameter by Speed Grade - DDR2-667 This chapter contains the AC Timing Parameters. Parameter Symbol DDR2-667 Min. Max. +450 +400 0.52 0.52 8000 -- -- -- -- Unit Note1)2)3)4)5)6)7) 8) tAC DQS output access time from CK / CK tDQSCK Average clock high pulse width tCH.AVG Average clock low pulse width tCL.AVG Average clock period tCK.AVG tDS.BASE DQ and DM input setup time DQ and DM input hold time tDH.BASE Control & address input pulse width for each input tIPW DQ and DM input pulse width for each input tDIPW Data-out high-impedance time from CK / CK tHZ DQS/DQS low-impedance time from CK / CK tLZ.DQS DQ low impedance time from CK/CK tLZ.DQ DQS-DQ skew for DQS & associated DQ signals tDQSQ CK half pulse width tHP DQ output access time from CK / CK DQ hold skew factor DQ/DQS output hold time from DQS Write command to DQS associated clock edges -450 -400 0.48 0.48 3000 100 175 0.6 0.35 -- ps ps 9) 1) 10)11) 10)11) tCK.AVG tCK.AVG ps ps ps 12)13)14) 1)1)15) tCK.AVG tCK.AVG ps ps ps ps ps ps ps nCK 1)16) 1)1) 1)1) 17) 18) tAC.MIN 2 x tAC.MIN -- Min(tCH.ABS, tCL.ABS) -- tAC.MAX tAC.MAX tAC.MAX 240 __ 340 -- + 0.25 -- -- -- -- 0.6 -- -- -- 1.1 0.6 70000 -- -- tQHS tQH WL 19) 20) tHP - tQHS RL-1 - 0.25 0.35 0.35 0.2 0.2 0.4 0.35 200 275 0.9 0.4 45 7.5 10 DQS latching rising transition to associated clock tDQSS edges DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Write postamble Write preamble Address and control input setup time Address and control input hold time Read preamble Read postamble Active to precharge command Active to active command period for 1KB page size products Active to active command period for 2KB page size products tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG ps ps 21) tDQSH tDQSL tDSS tDSH tWPST tWPRE tLS.BASE tLH.BASE tRPRE tRPST tRAS tRRD tRRD 1) 1) 22)23) 1)24) 25)26) 1)27) 28) 1) tCK.AVG tCK.AVG ns ns ns 1) Rev. 1.01, 2006-09 03292006-ZZHP-PR83 19 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules Parameter Symbol DDR2-667 Min. Max. -- -- -- -- -- -- -- -- -- -- -- -- -- 2 Unit Note1)2)3)4)5)6)7) 8) Four Activate Window for 1KB page size products tFAW Four Activate Window for 2KB page size products tFAW 37.5 50 2 15 WR + tnRP 7.5 7.5 ns ns nCK ns nCK ns ns ns nCK nCK nCK nCK nCK nCK ns ns nCK 1) 1) tCCD tWR Write recovery time Auto-Precharge write recovery + precharge time tDAL Internal write to read command delay tWTR Internal Read to Precharge command delay tRTP Exit self-refresh to a non-read command tXSNR Exit self-refresh to read command tXSRD Exit precharge power-down to any valid tXP CAS to CAS command delay command (other than NOP or Deselect) Exit power down to read command Exit active power-down mode to read command (slow exit, lower power) CKE minimum pulse width ( high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on (Power down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power down mode) ODT to power down entry latency ODT to power down exit latency Mode register set command cycle time MRS command to ODT update delay OCD drive mode output delay Minimum time clocks remain ON after CKE asynchronously drops LOW 1) 29)30) 1)31) 1) 1) tRFC +10 200 2 2 7 - AL 3 2 tXARD tXARDS tCKE tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD tMRD tMOD tOIT tDELAY 32) tAC.MIN tAC.MIN + 2 2.5 tAC.MAX + 0.7 2 x tCK.AVG + tAC.MAX + 1 2.5 1)33) tAC.MIN tAC.MIN + 2 3 8 2 0 0 tAC.MAX + 0.6 ns 2.5 x tCK.AVG + ns tAC.MAX + 1 -- -- 12 12 nCK nCK nCK ns ns ns 34)35) 1) 1) tLS + tCK .AVG + -- tLH 1) For details and notes see the relevant QIMONDA component data sheet 2) VDDQ = 1.8 V 0.1V; VDD = 1.8 V 0.1 V. See notes 1)1)1)1) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. Rev. 1.01, 2006-09 03292006-ZZHP-PR83 20 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 8) New units, `tCK.AVG` and `nCK`, are introduced in DDR2-667 and DDR2-800. Unit `tCK.AVG` represents the actual tCK.AVG of the input clock under operation. Unit `nCK` represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, `tCK` is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10PER).MIN = - 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN - tERR(6-10PER).MAX = - 400 ps - 293 ps = - 693 ps and tDQSCK.MAX(DERATED) = tDQSCK.MAX - tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2-667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps - 293 ps = - 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. 11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations). 12) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See Figure 3. 13) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS / DQS) crossing. 15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and VIH.DC.MIN. See Figure 3. 16) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . 17) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 18) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the minimum of the actual instantaneous clock low time. 19) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers. 20) tQH = tHP - tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 22) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied to the device under test. See Figure 4. 23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 24) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied to the device under test. See Figure 4. 25) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.PER.MIN = - 72 ps and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG - 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX + tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!). Rev. 1.01, 2006-09 03292006-ZZHP-PR83 21 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.DUTY.MIN = - 72 ps and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG - 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX + tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!). 28) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15 ns, the device will support tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter. 29) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2-533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 30) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR. 31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency. 32) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. 33) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 34) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. 35) When the device is operated with input clock jitter, this parameter needs to be derated by {-tJIT.DUTY.MAX - tERR(6-10PER).MAX} and {-tJIT.DUTY.MIN - tERR(6-10PER).MIN } of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10PER).MIN = - 272 ps, tERR(6- 10PER).MAX = + 293 ps, tJIT.DUTY.MIN = - 106 ps and tJIT.DUTY.MAX = + 94 ps, then tAOF.MIN(DERATED) = tAOF.MIN + {- tJIT.DUTY.MAX - tERR(6-10PER).MAX} = - 450 ps + {- 94 ps - 293 ps} = - 837 ps and tAOF.MAX(DERATED) = tAOF.MAX + {- tJIT.DUTY.MIN - tERR(6-10PER).MIN} = 1050 ps + {106 ps + 272 ps} = + 1428 ps. (Caution on the MIN/MAX usage!) FIGURE 2 Method for calculating transitions and endpoint VOH - x mV VOH - 2x mV tHZ tRPST end point VOL + 2x mV VOL + x mV T1 T2 VTT + 2x mV VTT + x mV tLZ tRPRE begin point VTT - x mV VTT - 2x mV T1 T2 tHZ,tRPST end point = 2*T1-T2 tLZ,tRPRE begin point = 2*T1-T2 Rev. 1.01, 2006-09 03292006-ZZHP-PR83 22 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules FIGURE 3 Differential input waveform timing - tDS and tDS DQS DQS tDS tDH tDS tDH VDDQ VIH(ac) min VIH(dc) min VREF(dc) VIL(dc) max VIL(ac) max VSS FIGURE 4 Differential input waveform timing - tlS and tlH CK CK tIS tIH tIS tIH VDDQ VIH(ac) min VIH(dc) min VREF(dc) VIL(dc) max VIL(ac) max VSS Rev. 1.01, 2006-09 03292006-ZZHP-PR83 23 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules TABLE 17 Timing Parameter by Speed Grade - DDR2-533 Parameter Symbol DDR2-533 Min. DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe) Max. +500 -- 0.55 -- 0.55 -- -- -- -- -- +450 -- 300 + 0.25 -- -- -- -- -- -- ps Unit Note1)2)3)4)5) 6)7) tAC tCCD tCH tCKE tCL tDAL tDELAY tDH(base) -500 2 0.45 3 0.45 WR + tRP tCK tCK tCK tCK tCK ns ps ps 8)21) tIS + tCK + tIH 225 -25 0.35 -450 0.35 -- - 0.25 100 -25 0.2 0.2 37.5 50 MIN. (tCL, tCH) -- 375 0.6 250 2 x tAC.MIN 9) 10) DQ and DM input hold time (single ended data tDH1(base) strobe) DQ and DM input pulse width (each input) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe) 11) tDIPW tDQSCK tDQSL,H tDQSQ tDQSS tDS(base) tCK ps tCK ps 11) tCK ps ps 11) DQ and DM input setup time (single ended data tDS1(base) strobe) DQS falling edge hold time from CK (write cycle) Four Activate Window period Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS 11) tDSH tCK tCK ns ns ps ps 13) 12) DQS falling edge to CK setup time (write cycle) tDSS tFAW tHP tHZ tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH tAC.MAX -- -- -- 13) 11) tCK ps ps ps 11) 14) 14) tAC.MIN 2 0 tAC.MAX tAC.MAX -- 12 -- tCK ns tHP -tQHS Rev. 1.01, 2006-09 03292006-ZZHP-PR83 24 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules Parameter Symbol DDR2-533 Min. Max. 400 7.8 3.9 -- -- -- -- -- -- 1.1 0.60 -- -- -- -- 0.60 -- Unit Note1)2)3)4)5) 6)7) Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Auto-Refresh to Active/Auto-Refresh command period Auto-Refresh to Active/Auto-Refresh command period Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble Write postamble Write recovery time for write without AutoPrecharge Write recovery time for write with AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command tQHS tREFI tRFC tRFC tRFC tRFC tRP tRP tRPRE tRPST tRRD tRTP tWPRE tWPST tWR WR -- -- -- 75 105 127.5 197.5 ps s s ns ns ns ns ns ns 14)15) 16)21) 17) 18) 19) 20) tRP + 1tCK 15 + 1tCK 0.9 0.40 7.5 10 7.5 0.25 x tCK 0.40 15 tCK tCK ns ns ns 14) 14) 14)21) 16)23) tCK tCK ns 22) tWR/tCK 7.5 2 6 - AL 2 -- -- -- -- -- -- tCK ns 23) tWTR tXARD tXARDS tXP tXSNR tXSRD 24) 25) tCK tCK tCK ns 25) tRFC +10 200 tCK 1) For details and notes see the relevant QIMONDA component data sheet 2) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V. See notes 5)6)7)8) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. Rev. 1.01, 2006-09 03292006-ZZHP-PR83 25 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) For timing definition, refer to the Component data sheet. 11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 14) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 15) 0 C TCASE 85 C 16) 85 C < TCASE 95 C 17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 18) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 19) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 20) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 21) The tRRD timing parameter depends on the page size of the DRAM organization. See. 22) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 23) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 24) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies 200 z. 25) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active powerdown mode" (MR, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MR, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied. Rev. 1.01, 2006-09 03292006-ZZHP-PR83 26 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules TABLE 18 Timing Parameter by Speed Grade - DDR2-400 Parameter Symbol DDR2-400 Min. DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe) Max. +600 -- 0.55 -- 0.55 -- -- -- -- -- +500 -- 350 + 0.25 -- -- -- -- -- -- ps Unit Note1)2)3)4)5) 6)7) tAC tCCD tCH tCKE tCL tDAL tDELAY tDH(base) -600 2 0.45 3 0.45 WR + tRP tCK tCK tCK tCK tCK ns ps ps 8)25) tIS + tCK + tIH 275 -25 0.35 -500 0.35 -- - 0.25 150 -25 0.2 0.2 37.5 50 MIN. (tCL, tCH) -- 475 0.6 350 2 x tAC.MIN 9) 10) DQ and DM input hold time (single ended data tDH1(base) strobe) DQ and DM input pulse width (each input) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) DQ and DM input setup time (differential data strobe) DQ and DM input setup time (single ended data strobe) DQS falling edge hold time from CK (write cycle) Four Activate Window period Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS 11) tDIPW tDQSCK tDQSL,H tDQSQ tCK ps tCK ps 11) Write command to 1st DQS latching transition tDQSS tCK ps ps 11) tDS(base) tDS1(base) tDSH 11) tCK tCK ns ns ps ps 13) 12) DQS falling edge to CK setup time (write cycle) tDSS tFAW tHP tHZ tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH tAC.MAX -- -- -- 13) 11) tCK ps ps ps 11) 14) 14) tAC.MIN 2 0 tAC.MAX tAC.MAX -- 12 -- tCK ns tHP -tQHS Rev. 1.01, 2006-09 03292006-ZZHP-PR83 27 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules Parameter Symbol DDR2-400 Min. Max. 450 7.8 3.9 -- -- -- -- -- -- 1.1 0.60 -- -- -- -- 0.60 -- Unit Note1)2)3)4)5) 6)7) Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Auto-Refresh to Active/Auto-Refresh command period Auto-Refresh to Active/Auto-Refresh command period Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble Write postamble Write recovery time for write without AutoPrecharge Write recovery time for write with AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command tQHS tREFI tRFC tRFC tRFC tRFC tRP tRP tRPRE tRPST tRRD tRTP tWPRE tWPST tWR WR -- -- -- 75 105 127.5 197.5 ps s s ns ns ns ns ns ns 14)15) 16)21) 17) 18) 19) 20) tRP + 1tCK 15 + 1tCK 0.9 0.40 7.5 10 7.5 0.25 x tCK 0.40 15 tCK tCK ns ns ns 14) 14) 14)21) 16)23) tCK tCK ns 22) tWR/tCK 10 2 6 - AL 2 -- -- -- -- -- -- tCK ns 23) tWTR tXARD tXARDS tXP tXSNR tXSRD 24) 25) tCK tCK tCK ns 25) tRFC +10 200 tCK 1) For details and notes see the relevant QIMONDA component data sheet 2) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V. See notes 5)6)7)8) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. Rev. 1.01, 2006-09 03292006-ZZHP-PR83 28 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) For timing definition, refer to the Component data sheet. 11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 14) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 15) 0 C TCASE 85 C 16) 85 C < TCASE 95 C 17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 18) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 19) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 20) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 21) The tRRD timing parameter depends on the page size of the DRAM organization. See . 22) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 23) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 24) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies 200 z. 25) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active powerdown mode" (MR, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MR, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied. 3.3.3 ODT AC Electrical Characteristics TABLE 19 ODT AC Characteristics and Operating Conditions for DDR2-667 This chapter contains the ODT AC electrical characteristics tables. Symbol Parameter / Condition Values Min. Max. 2 Unit Note tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency 2 tCK ns ns 1) tAC.MIN tAC.MIN + 2 ns 2.5 tAC.MAX + 0.7 ns 2 tCK + tAC.MAX + 1 ns 2.5 tCK ns ns 2) tAC.MIN tAC.MIN + 2 ns 3 8 tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns -- -- tCK tCK 1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Rev. 1.01, 2006-09 03292006-ZZHP-PR83 29 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules TABLE 20 ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400 Symbol Parameter / Condition Values Min. Max. 2 Unit Note tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency 2 tCK ns ns 1) tAC.MIN tAC.MIN + 2 ns 2.5 tAC.MAX + 1 ns 2 tCK + tAC.MAX + 1 ns 2.5 tCK ns ns 2) tAC.MIN tAC.MIN + 2 ns 3 8 tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns -- -- tCK tCK 1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Rev. 1.01, 2006-09 03292006-ZZHP-PR83 30 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 3.4 Currents Specifications and Conditions TABLE 21 IDD Measurement Conditions This chapter describes the Specifications and Conditions. Parameter Symbol Note1)2) 3)4)5)6) Operating Current 0 IDD0 One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current 1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. IDD1 Precharge Standby Current IDD2N All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING. Precharge Quiet Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. IDD2P IDD2Q IDD3N Active Power-Down Current IDD3P(0) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit); Active Power-Down Current IDD3P(1) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit); Operating Current Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Distributed Refresh Current tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. IDD4W IDD5B IDD5D Rev. 1.01, 2006-09 03292006-ZZHP-PR83 31 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules Parameter Symbol Note1)2) 3)4)5)6) Self-Refresh Current IDD6 CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 C max. All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0 mA. 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 3) Definitions for IDD see Table 22 4) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH. 5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P 6) For details and notes see the relevant QIMONDA component data sheet TABLE 22 Definitions for IDD Parameter LOW STABLE FLOATING SWITCHING Description VIN VIL(ac).MAX, HIGH is defined as VIN VIH(ac).MIN inputs are stable at a HIGH or LOW level inputs are VREF = VDDQ /2 inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes Rev. 1.01, 2006-09 03292006-ZZHP-PR83 32 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules TABLE 23 IDD Specification for HYS72T[32/64]xxxHP-[3S/3.7]-A HYS72T32000HP-3.7-A HYS72T64001HP-3.7-A HYS72T32000HP-3S-A HYS72T64001HP-3S-A HYS72T64020HP-3S-A Product Type HYS72T64020HP-3.7-A Unit Note1) Organization 256 MByte 1 Rank x72 -3S 512 MByte 1 Rank x72 -3S Max. 1710 1870 1410 690 1140 1410 940 690 2580 2670 2310 700 72 3080 512 MByte 2 Rank x72 -3S Max. 990 1070 1200 480 930 1200 730 480 1420 1470 1290 490 72 256 MByte 1 Rank x72 -3.7 Max. 830 870 650 370 560 650 470 370 960 1100 1100 380 36 512 MByte 1 Rank x72 -3.7 Max. 1490 1580 1130 570 950 1130 790 570 1760 2030 2030 610 72 512 MByte 2 Rank x72 -3.7 Max. 860 910 960 400 780 960 620 400 1000 1130 1130 440 72 mA mA mA mA mA mA mA mA mA mA mA mA mA 2) 2) 3) 3) 3) 3) 3) 3) 2) 2) 2) 3)4) 3)4) Symbol Max. 940 1020 790 430 660 790 560 430 1380 1420 1240 440 36 1630 2) 1670 1550 2930 1580 mA 1) Module IDD is calculated on the basis of component IDD and includes currents of Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P.MRS=0 IDD3P.MRS=1 IDD4R IDD4W IDD5B IDD5D IDD6 IDD7 defined with the outputs disabled. 2) The other rank is IDD2P Precharge Power-Down Standby Current mode. 3) Both ranks are in the same IDD mode. 4) Values for 0 C TCASE 85 C Rev. 1.01, 2006-09 03292006-ZZHP-PR83 33 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 3.4.1 Currents Test Conditions TABLE 24 IDD Measurement Test Conditions for DDR2-667 For testing the IDD parameters, the following timing parameters are used: Parameter Symbol -3S DDR2-667D Unit CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B command delay Active to Precharge Command Precharge Command Period Average periodic Refresh interval CL(IDD) 5 3.75 15 60 7.5 45 70000 15 7.8 tCK ns ns ns ns ns ns ns s tCK(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD) tRAS.MIN(IDD) tRAS.MAX(IDD) tRP(IDD) tREFI TABLE 25 IDD Measurement Test Conditions for DDR2-533 Parameter Symbol -3.7 DDR2-533C CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B command delay Active to Precharge Command Precharge Command Period Average periodic Refresh interval CL(IDD) 4 3.75 15 60 7.5 45 70000 15 7.8 Unit tCK ns ns ns ns ns ns ns s tCK(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD) tRAS.MIN(IDD) tRAS.MAX(IDD) tRP(IDD) tREFI Rev. 1.01, 2006-09 03292006-ZZHP-PR83 34 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 3.4.2 On Die Termination (ODT) Current The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A[6,2] in the EMRS(1) a "weak" or "strong" termination can be selected. The current consumption for any terminated input pin, depends on the input pin is in tri-state or driving 0 or 1, as long a ODT is enabled during a given period of time. TABLE 26 ODT current per terminated pin Parameter Enabled ODT current per DQ ODT is HIGH; Data Bus inputs are FLOATING Active ODT current per DQ ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING. Symbol Min. 5 2.5 7.5 Typ. 6 3 9 12 6 18 Max. 7.5 3.75 15 7.5 22.5 Unit mA/DQ mA/DQ mA/DQ mA/DQ mA/DQ EMRS(1) State A6 = 0, A2 = 1 A6 = 1, A2 = 0 A6 = 1, A2 = 1 A6 = 0, A2 = 1 A6 = 1, A2 = 0 A6 = 1, A2 = 0 IODTO 11.25 mA/DQ IODTT 10 5 15 Rev. 1.01, 2006-09 03292006-ZZHP-PR83 35 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 4 SPD Codes This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables * Table 27 "SPD Codes for PC2-5300" on Page 36 * Table 28 "SPD Codes for PC2-4200" on Page 41 TABLE 27 SPD Codes for PC2-5300 HYS72T32000HP-3S-A HYS72T64000HP-3S-A Product Type HYS72T64020HP-3S-A 512MB x72 2 Ranks (x8) PC2-5300P-555 Rev. 1.2 HEX 80 08 08 0D 0A 61 48 00 05 30 45 06 82 08 08 Organization 256MB x72 1 Rank (x8) 512MB x72 1 Rank (x8) PC2-5300P-555 Rev. 1.2 HEX 80 08 08 0E 0A 60 48 00 05 30 45 06 82 08 08 Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level PC2-5300P-555 Rev. 1.2 HEX 80 08 08 0D 0A 60 48 00 05 30 45 06 82 08 08 tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Rev. 1.01, 2006-09 03292006-ZZHP-PR83 36 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules HYS72T32000HP-3S-A HYS72T64000HP-3S-A Product Type Organization 256MB x72 1 Rank (x8) 512MB x72 1 Rank (x8) PC2-5300P-555 Rev. 1.2 HEX 00 0C 04 38 01 01 04 03 3D 50 50 60 3C 1E 3C 2D 80 20 27 10 17 3C 1E 1E 00 00 3C 512MB x72 2 Ranks (x8) PC2-5300P-555 Rev. 1.2 HEX 00 0C 04 38 01 01 05 03 3D 50 50 60 3C 1E 3C 2D 40 20 27 10 17 3C 1E 1E 00 00 3C Label Code JEDEC SPD Revision Byte# 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Description Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes PC2-5300P-555 Rev. 1.2 HEX 00 0C 04 38 01 01 04 03 3D 50 50 60 3C 1E 3C 2D 40 20 27 10 17 3C 1E 1E 00 00 3C tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns] Module Density per Rank tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] Analysis Characteristics tRC and tRFC Extension tRC.MIN [ns] Rev. 1.01, 2006-09 03292006-ZZHP-PR83 37 HYS72T64020HP-3S-A Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules HYS72T32000HP-3S-A HYS72T64000HP-3S-A Product Type Organization 256MB x72 1 Rank (x8) 512MB x72 1 Rank (x8) PC2-5300P-555 Rev. 1.2 HEX 69 80 18 22 0F 53 78 4B 2E 26 26 2B 1B 4A 20 22 C4 8C 68 94 12 47 7F 7F 7F 7F 7F 512MB x72 2 Ranks (x8) PC2-5300P-555 Rev. 1.2 HEX 4B 80 18 22 0F 52 82 43 25 29 25 2F 19 44 17 22 C4 8C 68 94 12 D7 7F 7F 7F 7F 7F Label Code JEDEC SPD Revision Byte# 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Description PC2-5300P-555 Rev. 1.2 HEX 4B 80 18 22 0F 52 82 43 25 29 25 2F 19 44 17 22 C4 8C 68 94 12 D5 7F 7F 7F 7F 7F tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns] PLL Relock Time TCASE.MAX Delta / T4R4W Delta Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Rev. 1.01, 2006-09 03292006-ZZHP-PR83 38 HYS72T64020HP-3S-A Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules HYS72T32000HP-3S-A HYS72T64000HP-3S-A Product Type Organization 256MB x72 1 Rank (x8) 512MB x72 1 Rank (x8) PC2-5300P-555 Rev. 1.2 HEX 51 00 00 xx 37 32 54 36 34 30 30 30 48 50 33 53 41 20 20 20 20 20 2x xx xx xx xx 512MB x72 2 Ranks (x8) PC2-5300P-555 Rev. 1.2 HEX 51 00 00 xx 37 32 54 36 34 30 32 30 48 50 33 53 41 20 20 20 20 20 2x xx xx xx xx Label Code JEDEC SPD Revision Byte# 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number PC2-5300P-555 Rev. 1.2 HEX 51 00 00 xx 37 32 54 33 32 30 30 30 48 50 33 53 41 20 20 20 20 20 2x xx xx xx xx Rev. 1.01, 2006-09 03292006-ZZHP-PR83 39 HYS72T64020HP-3S-A Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules HYS72T32000HP-3S-A HYS72T64000HP-3S-A Product Type Organization 256MB x72 1 Rank (x8) 512MB x72 1 Rank (x8) PC2-5300P-555 Rev. 1.2 HEX 00 FF 512MB x72 2 Ranks (x8) PC2-5300P-555 Rev. 1.2 HEX 00 FF Label Code JEDEC SPD Revision Byte# 128 255 Description Blank for customer use PC2-5300P-555 Rev. 1.2 HEX 00 FF 99 - 127 Not used Rev. 1.01, 2006-09 03292006-ZZHP-PR83 40 HYS72T64020HP-3S-A Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules TABLE 28 SPD Codes for PC2-4200 HYS72T32000HP-3.7-A HYS72T64000HP-3.7-A Product Type HYS72T64020HP-3.7-A 512MB x72 2 Ranks (x8) PC2-4200P-444 Rev. 1.2 HEX 80 08 08 0D 0A 61 48 00 05 3D 50 06 82 08 08 00 0C 04 38 01 01 05 03 3D Organization 256MB x72 1 Rank (x8) 512MB x72 1 Rank (x8) PC2-4200P-444 Rev. 1.2 HEX 80 08 08 0E 0A 60 48 00 05 3D 50 06 82 08 08 00 0C 04 38 01 01 04 03 3D Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level PC2-4200P-444 Rev. 1.2 HEX 80 08 08 0D 0A 60 48 00 05 3D 50 06 82 08 08 00 0C 04 38 01 01 04 03 3D tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes tCK @ CLMAX -1 (Byte 18) [ns] Rev. 1.01, 2006-09 03292006-ZZHP-PR83 41 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules HYS72T32000HP-3.7-A HYS72T64000HP-3.7-A Product Type Organization 256MB x72 1 Rank (x8) 512MB x72 1 Rank (x8) PC2-4200P-444 Rev. 1.2 HEX 50 50 60 3C 1E 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 0F 51 78 3F 22 512MB x72 2 Ranks (x8) PC2-4200P-444 Rev. 1.2 HEX 50 50 60 3C 1E 3C 2D 40 25 37 10 22 3C 1E 1E 00 00 3C 4B 80 1E 28 0F 55 82 37 1F Label Code JEDEC SPD Revision Byte# 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Description PC2-4200P-444 Rev. 1.2 HEX 50 50 60 3C 1E 3C 2D 40 25 37 10 22 3C 1E 1E 00 00 3C 4B 80 1E 28 0F 55 82 37 1F tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns] Module Density per Rank tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] Analysis Characteristics tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns] PLL Relock Time TCASE.MAX Delta / T4R4W Delta Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) Rev. 1.01, 2006-09 03292006-ZZHP-PR83 42 HYS72T64020HP-3.7-A Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules HYS72T32000HP-3.7-A HYS72T64000HP-3.7-A Product Type Organization 256MB x72 1 Rank (x8) 512MB x72 1 Rank (x8) PC2-4200P-444 Rev. 1.2 HEX 1E 1E 24 17 34 1E 20 C4 8C 61 78 12 19 7F 7F 7F 7F 7F 51 00 00 xx 37 32 54 36 34 512MB x72 2 Ranks (x8) PC2-4200P-444 Rev. 1.2 HEX 21 1D 28 14 2C 15 21 C4 8C 61 78 12 B2 7F 7F 7F 7F 7F 51 00 00 xx 37 32 54 36 34 Label Code JEDEC SPD Revision Byte# 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 Description T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 PC2-4200P-444 Rev. 1.2 HEX 21 1D 28 14 2C 15 21 C4 8C 61 78 12 B0 7F 7F 7F 7F 7F 51 00 00 xx 37 32 54 33 32 Rev. 1.01, 2006-09 03292006-ZZHP-PR83 43 HYS72T64020HP-3.7-A Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules HYS72T32000HP-3.7-A HYS72T64000HP-3.7-A Product Type Organization 256MB x72 1 Rank (x8) 512MB x72 1 Rank (x8) PC2-4200P-444 Rev. 1.2 HEX 30 30 30 48 50 33 2E 37 41 20 20 20 20 2x xx xx xx xx 00 FF 512MB x72 2 Ranks (x8) PC2-4200P-444 Rev. 1.2 HEX 30 32 30 48 50 33 2E 37 41 20 20 20 20 2x xx xx xx xx 00 FF Label Code JEDEC SPD Revision Byte# 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 128 255 Description Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number Blank for customer use PC2-4200P-444 Rev. 1.2 HEX 30 30 30 48 50 33 2E 37 41 20 20 20 20 2x xx xx xx xx 00 FF 99 - 127 Not used Rev. 1.01, 2006-09 03292006-ZZHP-PR83 44 HYS72T64020HP-3.7-A Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 5 Package Outlines FIGURE 5 Package Outline Raw Card F L-DIM-240-11 This chapter contains the package outlines of the products. Notes 1. General tolerances +/- 0.15 2. Drawing according to ISO 8015 Rev. 1.01, 2006-09 03292006-ZZHP-PR83 45 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules FIGURE 6 Package Outline Raw Card G L-DIM-240-12 Notes 1. General tolerances +/- 0.15 2. Drawing according to ISO 8015 Rev. 1.01, 2006-09 03292006-ZZHP-PR83 46 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules FIGURE 7 Package Outline Raw Card H L-DIM-240-13 Notes 1. General tolerances +/- 0.15 2. Drawing according to ISO 8015 Rev. 1.01, 2006-09 03292006-ZZHP-PR83 47 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules 6 Product Type Nomenclature Qimonda's nomenclature uses simple coding combined with some propriatory coding. Table 29 provides examples for module and component product type number as well as the field number. The detailed field description together with possible values and coding explanation is listed for modules in Table 30 and for components in Table 31. TABLE 29 Nomenclature Fields and Examples Example for Field Number 1 Micro-DIMM DDR2 DRAM HYS HYB 2 64 18 3 T T 4 64/128 512/ 5 0 16 6 2 7 0 0 8 K A 9 M C 10 -5 -5 11 -A TABLE 30 DDR2 DIMM Nomenclature Field 1 2 3 4 Description Qimonda Module Prefix Module Data Width [bit] DRAM Technology Memory Density per I/O [Mbit]; Module Density1) Values HYS 64 72 T 32 64 128 256 512 5 6 7 8 9 Raw Card Generation Number of Module Ranks Product Variations Package, Lead-Free Status Module Type 0 .. 9 0, 2, 4 0 .. 9 A .. Z D M R U F Coding Constant Non-ECC ECC DDR2 256 MByte 512 MByte 1 GByte 2 GByte 4 GByte Look up table 1, 2, 4 Look up table Look up table SO-DIMM Micro-DIMM Registered Unbuffered Fully Buffered Rev. 1.01, 2006-09 03292006-ZZHP-PR83 48 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules Field 10 Description Speed Grade Values -2.5F -2.5 -3 -3S -3.7 -5 Coding PC2-6400 5-5-5 PC2-6400 6-6-6 PC2-5300 4-4-4 PC2-5300 5-5-5 PC2-4200 4-4-4 PC2-3200 3-3-3 First Second 11 Die Revision -A -B 1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding". TABLE 31 DDR2 DRAM Nomenclature Field 1 2 3 4 Description Qimonda Component Prefix Interface Voltage [V] DRAM Technology Component Density [Mbit] Values HYB 18 T 256 512 1G 2G 5+6 Number of I/Os 40 80 16 7 8 9 10 Product Variations Die Revision Package, Lead-Free Status Speed Grade 0 .. 9 A B C F -25F -2.5 -3 -3S -3.7 -5 Coding Constant SSTL_18 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 Look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 4-4-4 DDR2-667 5-5-5 DDR2-533 4-4-4 DDR2-400 3-3-3 Rev. 1.01, 2006-09 03292006-ZZHP-PR83 49 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Performance table for -3S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Performance table for -3.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Performance table for -5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering Information for RoHS Compliant Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Address Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Components on Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration of RDIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Supply Voltage Levels and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Speed Grade Definition Speed Bins for DDR2-667D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Speed Grade Definition Speed Bins for DDR2-533C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Timing Parameter by Speed Grade - DDR2-667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Timing Parameter by Speed Grade - DDR2-533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Timing Parameter by Speed Grade - DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ODT AC Characteristics and Operating Conditions for DDR2-667. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . 30 IDD Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Definitions for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 IDD Specification for HYS72T[32/64]xxxHP-[3S/3.7]-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 IDD Measurement Test Conditions for DDR2-667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 IDD Measurement Test Conditions for DDR2-533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ODT current per terminated pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SPD Codes for PC2-5300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 SPD Codes for PC2-4200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Nomenclature Fields and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DDR2 DIMM Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DDR2 DRAM Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Rev. 1.01, 2006-09 03292006-ZZHP-PR83 50 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Pin Configuration for RDIMM (240 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Method for calculating transitions and endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential input waveform timing - tDS and tDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential input waveform timing - tlS and tlH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline Raw Card F L-DIM-240-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline Raw Card G L-DIM-240-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline Raw Card H L-DIM-240-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 22 23 23 45 46 47 Rev. 1.01, 2006-09 03292006-ZZHP-PR83 52 Internet Data Sheet HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules Table of Contents 1 1.1 1.2 2 2.1 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.1 3.4.2 4 5 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speed Grades Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Currents Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Currents Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 16 17 17 19 29 31 34 35 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Rev. 1.01, 2006-09 03292006-ZZHP-PR83 53 Internet Data Sheet Edition 2006-09 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com |
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